View 72V3631L15PFG8_8958711.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 june 2014 3.3 volt cmos syncfifo tm 512 x 36 1,024 x 36 idt72v3631 idt72v3641 2014 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-4658/4 idt and the idt logo are registered trademark of integrated device technology, inc. syncfifo is a trademark of integrated devi ce technology, inc. commercial temperature range ? 1 mail 1 register input register output register clka csa w/ r a ena mba port-a control logic reset logic rst clkb csb w /rb enb mbb port-b control logic mbf1 or ae b 0 - b 35 4658 drw 01 mail 2 register write pointer read pointer status flag logic mbf2 ir af fs 0 /sd fs 1 / se n flag offset registers a 0 - a 35 10 sync retransmit logic rtm rfm ram array 512 x 36 1,024 x 36 36 features ? ? ? ? ? storage capacity: idt72v3631 - 512 x 36 idt72v3641 - 1,024 x 36 ? ? ? ? ? supports clock frequencies up to 67 mhz ? ? ? ? ? fast access times of 10ns ? ? ? ? ? free-running clka and clkb can be asynchronous or coinci- dent (permits simultaneous reading and writing of data on a single clock edge) ? ? ? ? ? clocked fifo buffering data from port a to port b ? ? ? ? ? synchronous read retransmit capability ? ? ? ? ? mailbox register in each direction ? ? ? ? ? programmable almost-full and almost-empty flags ? ? ? ? ? microprocessor interface control logic ? ? ? ? ? input ready (ir) and almost-full ( af ) flags synchronized by clka ? ? ? ? ? output ready (or) and almost-empty ( ae ) flags synchronized by clkb ? ? ? ? ? available in space-saving 120-pin thin quad flat package (tqfp) ? ? ? ? ? pin and functionally compatible versions of the 5v operating idt723631/723641 ? ? ? ? ? easily expandable in width and depth ? ? ? ? ? green parts are available, see ordering information description the idt72v3631/72v3641 are pin and functionally compatible versons of the idt723631/723641, designed to run off a 3.3v supply for exceptionally low- power consumption. these devices are monolithic high-speed, low-power, cmos clocked fifo memory. it supports clock frequencies up to 67 mhz and has read access times as fast as 10ns. the 512/1,024 x 36 dual-port sram fifo buffers data from port a to port b. the fifo memory has retransmit capability, which allows previously read data to be accessed again. the fifo operates in first word fall through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. functional block diagram
2 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 tqfp (png120, order code: pf) top view note: 1. nc ? no internal connection. description (continued) pin configuration b 35 b 34 b 33 b 32 gnd b 31 b 30 b 29 b 28 b 27 b 26 v cc b 25 b 24 gnd b 23 b 22 b 21 b 20 b 19 b 18 gnd b 17 b 16 v cc b 15 b 14 b 13 b 12 gnd a 35 a 34 a 33 a 32 v cc a 31 a 30 gnd a 29 a 28 a 27 a 26 a 25 a 24 a 23 gnd a 22 v cc a 21 a 20 a 19 a 18 gnd a 17 a 16 a 15 a 14 a 13 v cc a 12 4658 drw 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 gnd clka ena w/ r a csa ir or v cc af ae vcc mbf2 mba rst gnd fs0/sd fs1/ sen rtm rfm v cc nc mbb gnd mbf1 gnd csb w /rb enb clkb v cc b 11 b 9 b 10 b 7 b 8 b 6 b 0 b 1 b 2 b 3 b 4 b 5 gnd v cc gnd a 0 a 1 a 3 a 4 a 2 a 5 v cc gnd gnd gnd a 11 a 10 a 9 a 8 a 7 a 6 communication between each port may take place with two 36-bit mailbox registers. each mailbox register has a flag to signal when new mail has been stored. two or more devices may be used in parallel to create wider data paths. expansion is also possible in word depth. these devices are a clocked fifo, which means each port employs a synchronous interface. all data transfers through a port are gated to the low- to-high transition of a continuous (free-running) port clock by enable signals. the continuous clocks for each port are independent of one another and can be asynchronous or coincident. the enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. the input ready (ir) flag and almost-full ( af ) flag of the fifo are two-stage synchronized to clka. the output ready (or) flag and almost-empty ( ae ) flag of the fifo are two-stage synchronized to clkb. offset values for the almost-full and almost-empty flags of the fifo can be programmed from port a or through a serial input. the idt72v3631/72v3641 are characterized for operation from 0 c to 70 c. these devices are fabricated using high speed, submicron cmos technology.
3 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 pin description symbol name i/o description a0-a35 port-a data i/o 36-bit bidirectional data port for side a. ae almost-empty o programmable flag synchronized to clkb. it is low when the number of words in the fifo is less than or equal to flag the value in the almost-empty register (x). af almost-full o programmable flag synchronized to clka. it is low when the number of empty locations in the fifo is less than or flag equal to the value in the almost-full offset register (y). b0-b35 port-b data i/o 36-bit bidirectional data port for side b. clka port-a clock i clka is a continuous clock that synchronizes all data transfers through port-a and may be asynchronous or coincident to clkb. ir and af are synchronous to the low-to-high transition of clka. clkb port-b clock i clkb is a continuous clock that synchronizes all data transfers through port-b and may be asynchronous or coincident to clka. or and ae are synchronous to the low-to-high transition of clkb. csa port-a chip i csa must be low to enable a low-to-high transition of clka to read or write data on port-a. the a0-a35 select outputs are in the high-impedance state when csa is high. csb port-b chip i csb must be low to enable a low-to-high transition of clkb to read or write data on port-b. the b0-b35 select outputs are in the high-impedance state when csb is high. ena port-a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port-a. enb port-b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port-b. fs1/ flag-offset i fs1/ sen and fs0/sd are dual-purpose inputs used for flag offset register programming. during a device reset, sen , select 1/ fs1/ sen and fs0/sd selects the flag offset programming method. three offset register programming methods are serial enable available: automatically load one of two preset values, parallel load from port a, and serial load. fs0/sd flag offset 0/ when serial load is selected for flag offset register programming, fs1/ sen is used as an enable synchronous to the serial data low-to-high transition of clka. when fs1/ sen is low, a rising edge on clka load the bit present on fs0/sd into the x and y registers. the number of bit writes required to program the offset registers is 18/20 for the idt72v3631/72v3641 respectively. the first bit write stores the y-register msb and the last bit write stores the x-register lsb. ir input ready o ir is synchronized to the low-to-high transition of clka. when ir is low, the fifo is full and writes to its arr ay flag are disabled. when the fifo is in retransmit mode, ir indicates when the memory has been filled to the point of the retransmit data and prevents further writes. ir is set low during reset and is set high after reset. mba port-a mailbox i a high level chooses a mailbox register for a port-a read or write operation. select mbb port-b mailbox i a high level chooses a mailbox register for a port-b read or write operation. when the b0-b35 outputs are act ive, select a high level on mbb selects data from the mail1 register for output and a low level selects fifo data for output. mbf1 mail1 register o mbf1 is set low by the low-to-high transition of clka that writes data to the mail1 register. mbf1 is set high by flag a low-to-high transition of clkb when a port-b read is selected and mbb is high. mbf1 is set high by a reset. mbf2 mail2 register o mbf2 is set low by the low-to-high transition of clkb that writes data to the mail2 register. mbf2 is set high by flag a low- to-high transition of clka when a port-a read is selected and mba is high. mbf2 is set high by a reset. or output ready o or is synchronized to the low-to-high transition of clkb. when or is low, the fifo is empty and reads are flag disabled. ready data is present in the output register of the fifo when or is high. or is forced low during the reset and goes high on the third low-to-high transition of clkb after a word is loaded to empty memory. rfm read from i when the fifo is in retransmit mode, a high on rfm enables a low-to-high transition of clkb to reset the read mark pointer to the beginning retransmit location and output the first selected retransmit data. rst reset i to reset the device, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst is low. the low-to-high transition of rst latches the status of fs0 and fs1 for af and ae offset selection. rtm retransmit i when rtm is high and valid data is present in the fifo output register (or is high), a low-to-high transition mode of clkb selects the data for the beginning of a retransmit and puts the fifo in retransmit mode. the selected word remains the initial retransmit point until a low- to-high transition of clkb occurs while rtm is low, taking the fifo out of retransmit mode. w/ r a port-a write/ i a high selects a write operation and a low selects a read operation on port a for a low-to-high transition of read select clka. the a0-a35 outputs are in the high-impedance state when w/ r a is high. w /rb port-b write/ i a low selects a write operation and a high selects a read operation on port b for a low-to-high transition of read select clkb. the b0-b35 outputs are in the high-impedance state when w /rb is low.
4 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (2) symbol rating commercial unit v cc supply voltage range ?0.5 to +4.6 v v i (2) input voltage range ?0.5 to v cc +0.5 (3) v v o (2) output voltage range ?0.5 to v cc +0.5 v i ik input clamp current, (v i < 0 or v i > v cc ) 20 ma i ok output clamp current, (v o = < 0 or v o > v cc ) 50 ma i out continuous output current, (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 400 ma t stg storage temperature range ?65 to 150 c idt72v3631 idt72v3641 commercial t clk = 15 ns symbol parameter test conditions min. typ. (1) max. unit v oh output logic "1" voltage v cc = 3.0v, i oh = ?4 ma 2.4 ? ? v v ol output logic "0" voltage v cc = 3.0v, i ol = 8 ma ? ? 0.5 v i li input leakage current (any input) v cc = 3.6v, v i = v cc or 0 ? ? 5 a i lo output leakage current v cc = 3.6v, v o = v cc or 0 ? ? 5 a i cc2 (2) standby current v cc = 3.6v, v i = v cc ?0.2v or 0 ? ? 400 a c in input capacitance v i = 0, f = 1 mhz ? 4 ? pf c out output capacitance v o = 0, f = 1 mhz ? 8 ? pf electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) notes: 1. all typical values are at v cc = 3.3v, t a = 25 c. 2. for additional i cc information, see figure 1, typical characteristics: supply current (i cc ) vs. clock frequency (f s ) . notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-m aximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3. control inputs: maximum v i = 5.0v. recommended operating conditions symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ih high level input voltage 2 ? v cc +0.5 v v il low-level input voltage ? ? 0.8 v i oh high-level output current ? ? ?4 ma i ol low-level output current ? ? 8 ma t a operating free-air 0 ? 70 c temperature
5 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 1. typical characteristics: supply current (i cc ) vs. clock frequency (f s ) determining active current consumption and power dissipation the i cc (f) current for the graph in figure 1 was taken while simultaneously reading and writing the fifo on the idt72v3641 with clka a nd clkb set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs w ere disconnected to normalize the graph to a zero-capacitance load. once the capacitance load per data-output channel and the number of idt72v3631/72v3641 i nputs driven by ttl high levels are known, the power dissipation can be calculated with the equation below. calculating power dissipation with i cc (f) taken from figure 1, the maximum power dissipation (pt) of these fifos may be calculated by: p t = v cc x i cc(f) + (c l x v cc 2 x f o ) n where: n = number of outputs = 36 c l = output capacitance load f o = switching frequency of an output when no reads or writes are occurring on these devices, the power dissipated by a single clock (clka or clkb) input running at frequency f s is calculated by: p t = v cc x f s x 0.025 ma/mhz 010 203040506070 0 25 50 75 100 125 150 v cc = 3.3v f s clock frequency mhz i cc(f) supply current ma f data = 1/2 f s t a = 25 c c l = 0 pf v cc = 3.0v v cc = 3.6v 4658 drw 04 175
6 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 ac electrical characteristics over recommended ranges of supply voltage and operating free-air temperature idt72v3631l15 idt72v3641l15 symbol parameter min. max. unit f s clock frequency, clka or clkb ? 66.7 mhz t clk clock cycle time, clka or clkb 15 ? ns t clkh pulse duration, clka or clkb high 6 ? ns t clkl pulse duration, clka or clkb low 6 ? ns t ds setup time, a0-a35 before clka and b0-b35 before clkb 5?ns t ens1 setup time, ena to clka ; enb to clkb 5?ns t ens2 setup time, csa , w/ r a, and mba to clka ; 7?ns csb , w /rb, and mbb to clkb t rms setup time, rtm and rfm to clkb 6?ns t rsts setup time, rst low before clka or clkb (1) 5?ns t fss setup time, fs0 and fs1 before rst high 9 ? ns t sds (2) setup time, fs0/sd before clka 5?ns t sens (2) setup time, fs1/ sen before clka 5?ns t dh hold time, a0-a35 after clka and b0-b35 after clkb 0.5 ? ns t enh1 hold time, ena after clka ; enb after clkb 0.5 ? ns t enh2 hold time, csa , w/ r a, and mba after clka ; 0.5 ? ns csb , w /rb, and mbb after clkb t rmh hold time, rtm and rfm after clkb 0.5 ? ns t rsth hold time, rst low after clka or clkb (1) 5?ns t fsh hold time, fs0 and fs1 after rst high 0 ? ns t sph (2) hold time, fs1/ sen high after rst high 0 ? ns t sdh (2) hold time, fs0/sd after clka 0?ns t senh (2) hold time, fs1/ sen after clka 0?ns t skew1 (3) skew time, between clka and clkb for or and ir 9 ? ns t skew2 (3,4) skew time, between clka and clkb for ae and af 12 ? ns notes: 1. requirement to count the clock edge as one of at least four needed to reset a fifo. 2. only applies when serial load method is used to program flag offset registers. 3. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween clka cycle and clkb cycle. 4. design simulated, not tested.
7 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 ac electrical characteristics idt72v3631l15 idt72v3641l15 symbol parameter min. max. unit f s clock frequency, clka or clkb ? 66.7 mhz t a access time, clkb to b0-b35 2 10 ns t pir propagation delay time, clka to ir 1 8 ns t por propagation delay time, clkb to or 1 8 ns t pae propagation delay time, clkb to ae 18ns t paf propagation delay time, clka to af 18ns t pmf propagation delay time, clka to mbf1 08ns low or mbf2 high and clkb to mbf2 low or mbf1 high t pmr propagation delay time, clka to b0-b35 (1) 210ns and clkb to a0-a35 (2) t mdv propagation delay time, mbb to b0-b35 valid 2 10 ns t rsf propagation delay time, rst low to ae low 1 15 ns and af high t en enable time, csa and w/ r a low to a0-a35 2 10 ns active and csb low and w /rb high to b0-b35 active t dis disable time, csa or w/ r a high to a0-a35 at high impedance and 1 8 ns csb high or w /rb low to b0-b35 at high impedance notes: 1. writing data to the mail1 register when the b0-b35 outputs are active and mbb is high. 2. writing data to the mail2 register when the a0-a35 outputs are active and mba is high.
8 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 is complete, the x and y register values are loaded bitwise through the fs0/ sd input on each low-to-high transition of clka that the fs1/ sen input is low. there are 18- or 20-bit writes needed to complete the programming for the idt72v3631 or idt72v3641 respectively. the first-bit write stores the most significant bit of the y register, and the last-bit write stores the least significant bit of the x register. each register value can be programmed from 1 to 508 (idt72v3631) or 1 to 1,020 (idt72v3641). when the option to program the offset registers serially is chosen, the input ready (ir) flag remains low until all register bits are written. the ir flag is set high by the low-to-high transition of clka after the last bit is loaded to allow normal fifo operation. the timing diagram for serial load of offset registers can be found in figure 4. fifo write/read operation the state of the port-a data (a0-a35) outputs is controlled by the port-a chip select ( csa ) and the port-a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0- a35 outputs are active when both csa and w/ r a are low. data is loaded into the fifo from the a0-a35 inputs on a low-to-high transition of clka when csa and the port-a mailbox select (mba) are low, w/ r a, the port-a enable (ena), and the input ready (ir) flag are high (see table 2). writes to the fifo are independent of any concurrent fifo read. for the write cycle timing diagram, see figure 5. the port-b control signals are identical to those of port-a with the exception that the port-b write/read select ( w /rb) is the inverse of the port-a write/read select (w/ r a). the state of the port-b data (b0-b35) outputs is controlled by the port-b chip select ( csb ) and the port-b write/read select ( w /rb). the b0-b35 outputs are in the high-impedance state when either csb is high or w /rb is low. the b0-b35 outputs are active when csb is low and w /rb is high. data is read from the fifo to its output register on a low-to-high transition of clkb when csb and the port-b mailbox select (mbb) are low, w /rb, the port-b enable (enb), and the output ready (or) flag are high (see table 3). reads from the fifo are independent of any concurrent fifo writes. for the read cycle timing diagram, see figure 6. the setup- and hold-time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. if a port enable is low during a clock cycle, the port chip select and write/read select may change states during the setup- and hold time window of the cycle. when the or flag is low, the next data word is sent to the fifo output register automatically by the clkb low-to-high transition that sets the or flag high. when or is high, an available data word is clocked to the fifo output register only when a fifo read is selected by the port-b chip select ( csb ), write/read select ( w /rb), enable (enb), and mailbox select (mbb). signal description reset the idt72v3631/72v3641 is reset by taking the reset ( rst ) input low for at least four port-a clock (clka) and four port-b (clkb) low-to-high transitions. the reset input may switch asynchronously to the clocks. a reset initializes the memory read and write pointers and forces the input ready (ir) flag low, the output ready (or) flag low, the almost-empty ( ae ) flag low, and the almost-full ( af ) flag high. resetting the device also forces the mailbox flags ( mbf1 , mbf2 ) high. after a fifo is reset, its input ready flag is set high after at least two clock cycles to begin normal operation. a fifo must be reset after power up before data is written to its memory. the relevant fifo reset timing diagram can be found in figure 2. first word fall through mode (fwft) these devices operate in the first word fall through mode (fwft). this mode uses the output ready function (or) to indicate whether or not there is valid data at the data outputs (b0-b35). it also uses the input ready (ir) function to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to data outputs, no read request necessary. subsequent words must be accessed by performing a formal read operation. almost-empty flag and almost-full flag offset program- ming two registers in these devices are used to hold the offset values for the almost- empty and almost-full flags. the almost-empty ( ae ) flag offset register is labeled x, and the almost-full ( af ) flag offset register is labeled y. the offset register can be loaded with a value in three ways: one of two preset values are loaded into the offset registers, parallel load from port a, or serial load. the offset register programming mode is chosen by the flag select (fs1, fs0) inputs during a low-to-high transition on the rst input (see table 1). ? preset values if the preset value of 8 or 64 is chosen by the fs1 and fs0 inputs at the time of a rst low-to-high transition according to table 1, the preset value is automatically loaded into the x and y registers. no other device initialization is necessary to begin normal operation, and the ir flag is set high after two low- to-high transitions on clka. for the preset value loading timing diagram, see figure 2. ? parallel load from port a to program the x and y registers from port a, the device is reset with fs0 and fs1 low during the low-to-high transition of rst . after this reset is complete, the ir flag is set high after two low-to-high transitions on clka. the first two writes to the fifo do not store data in its memory but load the offset registers in the order y, x. each offset register of the idt72v3631 and idt72v3641 uses port-a inputs (a8-a0), (a9-a0), and (a10-a0), respec- tively. the highest number input is used as the most significant bit of the binary number in each case. each register value can be programmed from 1 to 508 (idt72v3631) and 1 to 1,020 (idt72v3641). after both offset registers are programmed from port a, subsequent fifo writes store data in the ram. the timing diagram for parallel load of offset registers can be found in figure 3. ? serial load to program the x and y registers serially, the device is reset with fs0/sd and fs1/ sen high during the low-to-high transition of rst . after this reset note: 1. x register holds the offset for ae ; y register holds the offset for af . fs1 fs0 rst x and y registers (1) hh serial load hl 64 lh 8 ll parallel load from port a table 1 ? ? ? ? ? flag programming
9 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 synchronized fifo flags each idt72v3631/72v3641 fifo flag is synchronized to its port clock through at least two flip-flop stages. this is done to improve the flags? reliability by reducing the probability of metastable events on their outputs when clka and clkb operate asynchronously to one another. or and ae are synchronized to clkb. ir and af are synchronized to clka. table 4 shows the relationship of each flag to the number of words stored in memory. output ready flag (or) the output ready flag of a fifo is synchronized to the port clock that reads data from its array (clkb). when the or flag is high, new data is present in the fifo output register. when the or flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. a fifo read pointer is incremented each time a new word is clocked to its output register. the state machine that controls an or flag monitors a write- pointer and read-pointer comparator that indicates when the fifo memory status is empty, empty+1, or empty+2. from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of three cycles of clkb. therefore, an or flag is low if a word in memory is the next data to be sent to the fifo output register and three clkb cycles have not elapsed since the time the word was written. the or flag of the fifo remains low until the third low-to-high transition of clkb occurs, simultaneously forcing the or flag high and shifting the word to the fifo output register. a low-to-high transition on clkb begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clkb cycle may be the first synchronization cycle (see figure 7). input ready flag (ir) the input ready flag of a fifo is synchronized to the port clock that writes data to its array (clka). when the ir flag is high, a memory location is free in the fifo to write new data. no memory locations are free when the ir flag is low and attempted writes to the fifo are ignored. each time a word is written to a fifo, its write pointer is incremented. the state machine that controls an ir flag monitors a write-pointer and read pointer comparator that indicates when the fifo memory status is full, full-1, or full-2. from the time a word is read from a fifo, its previous memory location is ready to be written in a minimum of three cycles of clka. therefore, an ir flag is low if less than two cycles of clka have elapsed since the next memory write location has been read. the second low-to-high transition on clka after the read sets the input ready flag high, and data can be written in the following cycle. a low-to-high transition on clka begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clka cycle may be the first synchronization cycle (see figure 8). almost-empty flag ( ae ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array (clkb). the state machine that controls an ae flag monitors a write-pointer and read-pointer comparator that indicates when the fifo memory status is almost-empty, almost-empty+1, or almost-empty+2. the almost-empty state is defined by the contents of register x. this register is loaded with a preset value during a fifo reset, programmed from port a, or programmed serially (see almost-empty flag and almost-full flag offset pro- csb w /rb enb mbb clkb data b (b0-a35) i/o port functions h x x x x input none l l l x x input none llhl input none llhh input mail2 write l h l l x output none lhhl output fifo read l h l h x output none lhhh output mail1 read (set mbf1 high) csa w/ r a ena mba clka data a (a0-a35) i/o port functions h x x x x input none l h l x x input none lhhl input fifo write lhhh input mail1 write l l l l x output none llhl output none l l l h x output none llhh output mail2 read (set mbf2 high) table 2 ? ? ? ? ? port-a enable function table table 3 ? ? ? ? ? port-b enable function table
10 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 synchronous retransmit the synchronous retransmit feature of these devices allow fifo data to be read repeatedly starting at a user-selected position. the fifo is first put into retransmit mode to select a beginning word and prevent ongoing fifo write operations from destroying retransmit data. data vectors with a minimum length of three words can retransmit repeatedly starting at the selected word. the fifo can be taken out of retransmit mode at any time and allow normal device operation. the fifo is put in retransmit mode by a low-to-high transition on clkb when the retransmit mode (rtm) input is high and or is high. the rising clkb edge marks the data present in the fifo output register as the first retransmit data. the fifo remains in retransmit mode until a low-to-high transition occurs while rtm is low. when two or more reads have been done past the initial marked retransmit word, a retransmit is initiated by a low-to-high transition on clkb when the read-from-mark (rfm) input is high. this rising clkb edge shifts the first retransmit word to the fifo output register and subsequent reads can begin immediately. retransmit loops can be done endlessly while the fifo is in retransmit mode. rfm must be low during the clkb rising edge that takes the fifo out of retransmit mode (see figure 11). when the fifo is put into retransmit mode, it operates with two read pointers. the current read pointer operates normally, incrementing each time when a new word is shifted to the fifo output register. this read pointer position is used by the or and ae flags. the shadow read pointer stores the memory location at the time the device is put into retransmit mode and does not change until the device is taken out of retransmit mode. the shadow read pointer position is used by the ir and af flags. data writes can proceed while the fifo is in retransmit mode, but af is set low by the write that stores (512-y) or (1,024-y) words after the first retransmit word for the idt72v3631 or idt72v3641 respectively. the ir flag is set low by the 512th or 1,024th write after the first retransmit word for the idt72v3631 or idt72v3641 respectively. when the fifo is in retransmit mode and rfm is high, a rising clkb edge loads the current read pointer with the shadow read-pointer value and the or flag reflects the new level of fill immediately. if the retransmit changes the fifo status out of the almost-empty range, up to two clkb rising edges after the retransmit cycle are needed to switch ae high (see figure 12). the rising clkb edge that takes the fifo out of retransmit mode shifts the read pointer used by notes: 1. when a word is present in the fifo output register, its previous memory location is free. 2. data in the output register does not count as a "word i n fifo memory". since in fwft mode, the first words written to an em pty fifo goes unrequested to the output register (no read operation necessary), it is not included in the memory count. 3. x is the almost-empty offset for ae . y is the almost-full offset for af . gramming section). the ae flag is low when the fifo contains x or less words and is high when the fifo contains (x+1) or more words. a data word present in the fifo output register has been read from memory. two low-to-high transitions of clkb are required after a fifo write for the ae flag to reflect the new level of fill; therefore, the ae flag of a fifo containing (x+1) or more words remains low if two cycles of clkb have not elapsed since the write that filled the memory to the (x+1) level. an ae flag is set high by the second low-to-high transition of clkb after the fifo write that fills memory to the (x+1) level. a low-to-high transition of clkb begins the first synchronization cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) words. otherwise, the subsequent clkb cycle may be the first synchronization cycle (see figure 9). almost-full flag ( af ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array (clka). the state machine that controls an af flag monitors a write-pointer and read-pointer comparator that indicates when the fifo memory status is almost-full, almost-full-1, or almost-full-2. the almost-full state is defined by the contents of register y. this register is loaded with a preset value during a fifo reset, programmed from port a, or programmed serially (see almost-empty flag and almost-full flag offset programming section). the af flag is low when the number of words in the fifo is greater than or equal to (512-y) or (1,024-y) for the idt72v3631 or idt72v3641 respectively. the af flag is high when the number of words in the fifo is less than or equal to [512-(y+1)] or [1,024-(y+1)] for the idt72v3631 or idt72v3641 respec- tively. a data word present in the fifo output register has been read from memory. two low-to-high transitions of clka are required after a fifo read for its af flag to reflect the new level of fill. therefore, the af flag of a fifo containing [512/1,024-(y+1)] or less words remains low if two cycles of clka have not elapsed since the read that reduced the number of words in memory to [512/ 1,024-(y+1)]. an af flag is set high by the second low-to-high transition of clka after the fifo read that reduces the number of words in memory to [512/1,024-(y+1)]. a low-to-high transition of clka begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of words in memory to [512/1,024-(y+1)]. otherwise, the subsequent clka cycle may be the first synchronization cycle (see figure 10). number of words in the fifo (1,2) synchronized synchronized to clkb to clka idt72v3631 (3) idt72v3641 (3) or ae af ir 00llhh 1 to x 1 to x h l h h (x+1) to [512-(y+1)] (x+1) to [1,024-(y+1)] h h h h (512-y) to 511 (1,024-y) to 1,023 h h l h 512 1,024 h h l l table 4 ? ? ? ? ? fifo flag operation
11 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 the ir and af flags from the shadow to the current read pointer. if the change of read pointer used by ir and af should cause one or both flags to transmit high, at least two clka synchronizing cycles are needed before the flags reflect the change. a rising clka edge after the fifo is taken out of retransmit mode is the first synchronizing cycle of ir if it occurs at time t skew1 or greater after the rising clkb edge (see figure 13). a rising clka edge after the fifo is taken out of retransmit mode is the first synchronizing cycle of af if it occurs at time t skew2 or greater after the rising clkb edge (see figure 14). mailbox registers two 36-bit bypass registers are on the idt72v3631/72v3641 to pass command and control information between port a and port b. the mailbox select (mba, mbb) inputs choose between a mail register and a fifo for a port data transfer operation. a low-to-high transition on clka writes a0-a35 data to the mail1 register when a port-a write is selected by csa , w/ r a, and ena with mba high. a low-to-high transition on clkb writes b0-b35 data to the mail2 register when a port-b write is selected by csb , w /rb, and enb with mbb high. writing data to a mail register sets its corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while its mail flag is low. when the port-b data (b0-b35) outputs are active, the data on the bus comes from the fifo output register when the port-b mailbox select (mbb) input is low and from the mail1 register when mbb is high. mail2 data is always present on the port-a data (a0-a35) outputs when they are active. the mail1 register flag ( mbf1 ) is set high by a low-to-high transition on clkb when a port- b read is selected by csb , w /rb, and enb with mbb high. the mail2 register flag (mbf2) is set high by a low-to-high transition on clka when a port- a read is selected by csa , w/ r a, and ena with mba high. the data in a mail register remains intact after it is read and changes only when new data is written to the register. mail register and mail register flag timing can be found in figure 15 and 16.
12 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 3. programming the almost-full flag and almost-empty flag offset values from port a note: 1. csa = low, w/ r a = high, mba = low. it is not necessary to program offset register on consecutive clock cycles. figure 2. fifo reset and loading x and y with a preset value of eight clka rst ir ae af mbf1 , mbf2 clkb or fs1,fs0 4658 drw 05 t rsts t rsth t fsh t fss t pir 0,1 t rsf t por t rsf t rsf t pir 4658 drw 06 clka rst ir a0 - a35 fs1,fs0 ena t enh1 t ens1 4 t pir first word stored in fifo ae offset (x) af offset (y) t fss t fsh t ds t dh
13 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 4. programming the almost-full flag and almost-empty flag offset values serially figure 6. fifo read cycle timing note: 1. it is not necessary to program offset register bits on consecutive clock cycles. fifo write attempts are ignored until ir is set high. figure 5. fifo write cycle timing clka rst ir fs1/ sen fs0/sd 4 af offset (y) msb ae offset (x) lsb 4658 drw 07 t fss t fss t fsh t sph t sens t senh t sds t sdh t sens t senh t sds t sdh t pir clka ir ena mba csa w/ r a t clkh t clkl t clk t ens2 t ens2 t ens2 t ens1 t enh2 t enh2 t enh2 t enh1 t ens1 t enh1 t enh1 t ens1 4658 drw 08 a0 - a35 t ds t dh w1 w2 no operation high 4658 drw 09 clkb or enb b0 - b35 mbb csb w /rb t clk t clkh t clkl t ens1 t a t mdv t en t a t ens1 t enh1 t ens1 t enh1 w1 w2 w3 t enh1 t dis no operation high
14 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 7. or flag timing and first data word fall through when the fifo is empty note: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for or to transition high and to clock the next word to the fifo output register in three clkb cycles. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of or high and the first word load to the output register may occur one clkb cycle later than shown. csa w/ r a mba ir a0 - a35 clkb or csb w /rb mbb ena enb b0 -b35 clka 12 3 4658 drw 10 t clkh t clkl t clk t ens2 t ens1 t enh2 t enh1 t ds t dh t skew1 t clk t clkl t por t por t ens1 t enh1 t a old data in fifo output register w1 fifo empty low high low high low t clkh w1 high (1)
15 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 9. timing for ae ae ae ae ae when fifo is almost-empty figure 8. ir flag timing and first available write when the fifo is full note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ir to transition high in the next clka cycle. if th e time between the rising clkb edge and rising clka edge is less than t skew1 , then ir may transition high one clka cycle later than shown. notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for ae to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then ae may transition high one clkb cycle later than shown. 2. fifo write ( csa = low, w/ r a = high, mba = low), fifo read ( csb = low, w /rb = high, mbb = low). csb or w /rb mbb enb b0 - b35 clkb ir clka csa w/ r a a0 - a35 mba ena 4658 drw 11 12 t clk t clkh t clkl t ens1 t enh1 t a t skew1 t clk t clkh t clkl t pir t pir t ens2 t ens1 t ds t enh2 t enh1 t dh previous word in fifo output register next word from fifo low high low high low high (1) fifo full write ae clka enb ena clkb 4658 drw 12 2 1 t ens1 t enh1 t skew2 t pae t pae t ens1 t enh1 x word in fifo (x+1) words in fifo (1)
16 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for af to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then af may transition high one clka cycle later than shown. 2. depth is 512 for the idt72v3631 and 1,024 for the idt72v3641. 3. fifo write ( csa = low, w/ r a = high, mba = low), fifo read ( csb = low, w /rb = high, mbb = low). figure 10. timing for af af af af af when fifo is almost-full figure 12. ae ae ae ae ae maximum latency when retransmit increases the number of stored words above x. note: 1. x is the value loaded in the almost-empty flag offset register. note: 1. csb = low, w/rb = high, mbb = low. no input enables other than rtm and rfm are needed to control retransmit mode or begin a retransmit. other enables are shown only to relate retransmit operations to the fifo output register. figure 11. retransmit timing showing minimum retransmit length af clka enb ena clkb 4658 drw 13 12 t skew2 t ens1 t enh1 t paf t ens1 t enh1 t paf (1) [depth -(y+1)] words in fifo (2) (depth -y) words in fifo (2) clkb enb rtm rfm or b0-b35 w0 w1 w2 w0 w1 high t a t a t a t a initiate retransmit mode with w0 as first word retransmit from selected position end retransmit mode 4658 drw 14 t ens1 t enh1 t rms t rmh t rms t rmh t rms t rmh clkb rtm rfm ae t pae x or fewer words from empty (x+1) or more words from empty 4658 drw 15 t rms t rmh 1 2 high
17 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ir to transition high in the next clka cycle. if th e time between the rising clkb edge and rising clka edge is less than t skew1 , then ir may transition high one clka cycle later than shown. figure 13. ir timing from the end of retransmit mode when one or more write locations are available notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for af to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then af may transition high one clka cycle later than shown. 2. depth is 512 for the idt72v3631 and 1,024 for the idt72v3641. 3. y is the value loaded in the almost-full flag offset register. figure 14. af af af af af timing from the end of retransmit mode when (y+1) or more write locations are available figure 15. timing for mail1 register and mbf1 mbf1 mbf1 mbf1 mbf1 flag t skew1 clka ir clkb rtm fifo filled to first restransmit word 1 2 one or more write locations available 4658 drw 16 (1) t pir t rms t rmh clka af clkb rtm t skew2 (depth -y) or more words past first restransmit word 1 2 (y+1) or more write locations available 4658 drw 17 (1) t pae t rms t rmh (2) 4658 drw 18 clka ena a0 - a35 mba csa w/ r a clkb mbf1 csb mbb enb b0 - b35 w /rb w1 t ens2 t enh2 t ds t dh t pmf t pmf t en t mdv t pmr t ens1 t enh1 t dis w1 (remains valid in mail1 register after read) fifo output register t ens2 t enh2 t ens2 t enh2 t ens2 t enh2
18 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 figure 16. timing for mail2 mail2 mail2 mail2 mail2 register and mbf2 mbf2 mbf2 mbf2 mbf2 flag figure 17. block diagram of 512 x 36, 1,024 x 36 synchronous fifo memory with programmable flags used in depth expansion configuration notes: 1. mailbox feature is not supported in depth expansion applications. (mba + mbb tie to gnd) 2. transfer clock should be set either to the write port clock (clka) or the read port clock (clkb), whichever is faster. 3. retransmit feature is not supported in depth expansion applications. 4. the amount of time it takes for or of the last fifo in the chain to go high (i.e. valid data to appear on the last fifo?s out puts) after a word has been written to the first fifo is the sum of the delays for each individual fifo: (n - 1)*(4*transfer clock) + 3*t rclk , where n is the number of fifos in the expansion and t rclk is the clkb period. 5. the amount of time is takes for ir of the first fifo in the chain to go high after a word has been read from the last fifo is the sum of the delays for each individual fifo: (n - 1)*(3*transfer clock) + 2*t wclk , where n is the number of fifos in the expansion and t wclk is the clka period. 4658 drw 19 clkb enb b0 - b35 mbb csb w /rb clka mbf2 csa mba ena a0 - a35 w/ r a w1 t ens2 t enh2 t ds t dh t pmf t pmf t ens1 t enh1 t dis t en t pmr w1 (remains valid in mail2 register after read) t ens2 t enh2 t ens2 t enh2 t ens2 t enh2 data in (dn) read clock (clkb) read enable (enb) output ready (or) chip select ( csb ) data out (qn) transfer clock 4658 drw 20 idt 72v3631 72v3641 v cc write read a 0 -a 35 mba chip select ( csa ) write select (w/ r a) write enable (ena) almost-full flag ( af ) input ready (ir) write clock (clka) clkb or enb csb b 0 -b 35 w/ r b mbb clka ena ir csa mba a 0 -a 35 w/ r a read select (w/ r b) almost-empty flag ( ae ) b 0 -b 35 mbb n n n qn dn v cc v cc v cc idt 72v3631 72v3641
19 commercial temperature range idt72v3631/72v3641 3.3v cmos syncfifo? 512 x 36 and 1,024 x 36 note: 1. includes probe and jig capacitance figure 18. load circuit and voltage waveforms 4658 drw 21 parameter measurement information from output under test 30 pf 330 3.3v 510 3 v gnd timing input data, enable input gnd 3 v 1.5 v 1.5 v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times 3 v gnd gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v t w output enable low-level output high-level output 3 v ol gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v oh ov gnd oh ol 1.5 v 1.5 v 1.5 v 1.5 v input in-phase output high-level input low-level input v v v v 1.5 v 3 v t s t h t plz t phz t pzl t pzh t pd t pd (1)
20 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com ordering information blank commercial (0 c to +70 c) xxxxxx device type xx x power speed package clock cycle time (t clk ) speed in nanoseconds commercial only process/ temperature range xxx 15 x 4658 drw22 tube or tray tape and reel x blank 8 g pf l green thin quad flat pack (tqfp, png120) low power 72v3631 72v3641 512 x 36 3.3v syncfifo 1,024 x 36 3.3v syncfifo datasheet document history 07/31/2000 pgs. 1, 14, 21. 11/04/2003 pg. 1. 02/05/2009 pgs. 1 and 21. 06/18/2014 pgs. 1-20.

▲Up To Search▲

Price & Availability of 72V3631L15PFG8

	To Download 72V3631L15PFG8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .